Interpreting the RAMCHECK DDR2 Test Log for DDR2 Devices

INN-8668-APN29
--Created 2-6-08

1. The test log will be automatically displayed after the Basic test ends unless you press the "ESC" key to terminate the test.
2. You can press "F5" anytime during the Basic Test to view the test log.
3. The test log can be viewed anytime after you start the Basic test by simply pressing the "ESC" key after the Basic test is completed. Once in standby mode press "F4" then "F1" for "View Test Log", use "F4" to go forward through the screens and "F3" to go back. Once finished simply press the "ESC" key to go back to standby mode.
4. By installing the RAMCHECK PC Communications program that was included with your RAMCHECK on your PC and connecting your RAMCHECK to your computer via the serial cable you can view, save or print out the complete test log for future reference.

	BASIC TEST The test phase use by the RAMCHECK. DDR2 DUT DETECTED - UBF Describes the type of DUT (Device Under Test) that you are testing, in this case DDR2. "Type" is unbuffered display as "UBF", please see below. STRUCTURE TEST Starts a brief test to determine the structure of the DDR2 module. All information that follows is the structure of the DDR2 device as detected by the RAMCHECK.
	BANK BITS DETECTED: BANK 1: CB DQ63 - 32     DQ31 - 0 00 FFFFFFFF FFFFFFFF Gives you a brief description of the structure of the DDR2 device by mapping the DQ and CB (Parity) bits by the module's individual banks. This feature is very useful in troubleshooting DDR2 Modules with severe or multiple errors. Starts a brief test to determine the structure of the DDR2 module. All information that follows is the structure of the DDR2 device as detected by the RAMCHECK.
	CONNECTOR WIRING - OK At the start of the Basic Test the RAMCHECK performs a wiring test to verify that the Control lines are properly wired and functional. In this instance it reported no errors. DATA WIRING - PASS DQS WIRING - PASS ADD. WIRING - PASS At the start of the Basic Test the RAMCHECK performs a wiring test to verify that the Data, DQS and Address lines are properly wired and functional. In this case it reported no errors.
	TEST AT SSTL 1.9V The DDR2 module is being tested at 1.9 volts. SIZE: 64Mx64=512M Shows the size of the DDR2 module in both JEDEC notation and overall size. CHIP SIZE: 4x16Mx8=64Mx8 Shows the size of the individual DDR2 chips of the DDR2 module in both JEDEC notation and overall size.
	14 ROW/10 COL ADDR. Shows the number of rows and columns detected by the RAMCHECK. REFRESH:AUTO Shows that the refresh rate is in Auto mode which will use the RAMCHECK's default value. BANKS: 1 -S:0 Shows a brief description of the structure of the DDR2 module similar to the "BANKS BITS DETECTED" shown above, but by displaying the number of banks and individual control lines that were detected by the RAMCHECK.
	DQS:8..0 DM: 8..0 Detects the use of either 8/9 pairs of DQS lines and 8/9 DM lines or only 18 pairs of DQS lines. SPD=JEDEC Conforms to JEDEC standards. DDR2 240P DIMM Shows the form factor of the DDR2 module, in this case a 240-pin DIMM. TEST TABLE #26 The "TEST TABLE" and "CODE" (display in the screen below) indications are used as part of our factory development to identify certain characteristics of the DDR2 device. These identifications can also be used as a form of comparison to other DDR2 devices.
	CODE=1067 TYPE: UNBUFFERED The RAMCHECK detected the DDR2 module as conforming to the JEDEC standard for Unbuffered configurations. Other types may include Registered, etc. ECC=N The RAMCHECK detected that this DDR2 module does not have (ECC) Error Correction Code wiring. If "ECC=Y" was displayed then ECC would have been detected. CLOCKS:3 CK0+1+2 The RAMCHECK detected the use three clock inputs and displayed which clock inputs it detected.
	BL TEST=4, 8 - OK The RAMCHECK tested the operation of the two burst lengths available in DDR2 devices, 4 and 8. In this instance it indicates that BL (Burst Length) tested ok on both. SPD=CL4 - 667MHz SPD=CL3 - 533MHz SPD=PC5400 Any time you see "SPD=" in the test log, it always refers to the information read directly from the SPD chip on the DDR2 device which is programmed by the module's manufacturer. In this case the SPD claims that this module is a PC5400 (667 MHz @ CL4). You can also view the "SPEED TEST RESULT" describe below to see if the SPD information compares with the RAMCHECK's test results.
	ARRAY TEST @CL4 Ends the "STRUCTURE TEST" and starts the "ARRAY TEST @ CL4" where the entire memory array is written and verified twice at CL=4 to catch most cell stuck problems. ARRAY TEST - OK No errors were detected at CL4 SPEED TEST RESULT: TEST=PC2-5400 The RAMCHECK determined that this DDR2 module is within PC5400 specifications
	FINAL SPEED:667MHz Final speed detected at the end of the Basic Test BASIC TEST OK Shows that the DDR2 device passed the Basic Test TIME: 00:14.6 Displays the time it took to complete the test in minutes and seconds

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