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RAMCHECK DDR Series Manual Addendum

DDR memory tester adapter

The RAMCHECK line provides comprehensive support for testing DDR DIMM modules using the RAMCHECK DDR 184-Pin Adapter (p/n INN-8668-6). We have also introduced the RAMCHECK Plus as a combination package of RAMCHECK and this adapter. This manual addendum describes the operation of this adapter as well as the DDR S.O. DIMM Converter.


This adapter connects to RAMCHECK via the two top 90-pin and 50-pin expansion slots. Turn RAMCHECK OFF and carefully mount the adapter onto RAMCHECK expansion slots, while pressing it gradually on both sides.

CAUTION: Plug this adapter into the expansion slots only when RAMCHECK is OFF! Failure to turn RAMCHECK OFF when connecting or disconnecting the DDR 184-pin Adapter may result in damage to the internal PAL chips of both the RAMCHECK and the Adapter!

While the DDR adapter is installed on RAMCHECK, you can test only the 184-pin DDR modules. To test the 168-pin DIMM modules, the adapter must be removed. Please turn RAMCHECK OFF and carefully remove the DDR adapter, by gradually pulling it up on both sides, taking care not to flex the adapter's boards.

CAUTION:Please let the adapter COOL DOWN for at least 30 seconds before attempting to remove it from RAMCHECK. Removal of the adapter while hot may impair some soldered connections of its delicate internal parts!
                with the DDR adapter

RAMCHECK automatically recognizes the presence of the DDR Adapter with the following turn-on screen:

Required RAMCHECK Firmware Version:2.14E or later. Newer, pre-release version might be available at the Beta Program section of our download page.


The DDR 184-Pin Adapter supports the new 184-pin DDR DIMM modules. While these modules are similar in size to the 168-Pin SDRAM DIMM modules, they have only one key area (small area in the module's connector without contacts) as compared to two key areas for the SDRAM modules. And of course, the DDR module has 92 pins on each side of the connector compared to 84 pins on the SDRAM module. Facing the DDR module from the front, the key area is located between pins 52 and 53.

INSERTION: The DDR 184-Pin Adapter uses a vertically mounted high quality test socket with two ejectors that need to be opened prior to insertion. Carefully insert the DDR DIMM into the socket, pushing it evenly along its top. Pin 1 of the module should point to the left side (as marked on the adapter), so that the key area of the module's connector is correctly aligned with the key area in the test socket. When the DIMM is properly inserted, the ejectors will snap onto the half circle notches on each side of the module.

REMOVAL: The DIMM is easily released from the socket by pulling both ejectors sideways.

NOTE: DIMM insertion and removal should be done only when RAMCHECK is in STANDBY Mode. The RED "Module Power" LED should be OFF in STANDBY mode.


Turn RAMCHECK ON once the DDR 184-pin Adapter is installed and insert the first DIMM module. THERE IS NO NEED TO SETUP RAMCHECK, as it automatically recognizes the DDR adapter. When RAMCHECK enters the STANDBY mode, the display will prompt you to test DDR modules.

The DDR test procedure is initiated by pressing the F1 key and is designed to follow the regular RAMCHECK test flows. Unless your press the ESC key, EXTENSIVE TEST follows BASIC TEST, and AUTO-LOOP follows BASIC TEST.


At the start of Basic Test, RAMCHECK provides power and proper initialization sequence (involving control and clock lines) to the DDR module. A large variety of quick wiring tests are conducted, the module structure and frequency is determined, and the memory array tests begin for both CL=2 and CL=2.5 (CL stands for CAS Latency). Since the wiring and structure tests are extremely fast, their results are logged in the Test Log and reported after the end of Basic Test, unless an error is encountered, as shown below. Before discussion the wiring and structure test results, let us review the two main phases of Basic Test, the memory array tests at CL=2 and CL=2.5. These array tests take the bulk of the time of the Basic Test.

Memory Array Test at CL=2

The following screen shows the information provided during the first main phase of Basic Test - the array test for CL=2:

In this example, a 64Mx64 Unbuffered (marked UBF) module is tested at CL=2. The entire memory array is written and verified twice to catch most memory cell stuck problems. The marker to the right of the UBF message indicates that the test is at 2.5V.

The "B2/3" marker at the bottom right corner is the "section under test" indicator, which has been modified for DDR devices. With DDR devices, each chip has four internal banks, which are selected by the BA1 and BA0 bank address lines. The module itself may have one or two main banks which are selected by S0 and S1 control lines. In this example, "B2/3" indicates that the section under test is the module's main bank 2 and the internal chips bank 3. If the marker was "B1/0", it would indicate main bank 1 and internal chips bank 0. Similarly, "B1/2" would indicate main bank 1 and internal chips bank 2, and so on. Modules with only one main bank will scan "B1/0"->"B1/1"-> ... ->"B1/3", before switching to the next test pattern. Modules with two main banks will scan "B1/0"-> ... ->"B1/3"->"B2/0"->...->"B2/3" for each test pattern.

Memory Array Test at CL=2.5

After the completion of the first memory array test at CL=2, the second memory array test at CL=2.5 is conducted.

In this example (using a different module for the screen capture), a 32Mx72 Registered module is tested at 266MHz and at CL=2.5. Registered modules are marked by the "REG" reversed message.

Wiring tests at the start of Basic Test

At the start of Basic Test, RAMCHECK performs a large number of wiring tests to verify that data lines, address lines and control lines are properly wired and function.

If no wiring problems are detected, the above screen is written into the Test Log. In the event of errors, RAMCHECK stops the test and provides error indication as well as detailed information regarding the pin connection associated with the detected error. Error report styles are similar to other RAMCHECK error reports for SDRAM and EDO/FPM devices. The following screens provide some examples:

The above screen shows data line D8 (connector pin-12) stuck at logic '0'.

The above screen shows control line -WE (connector pin-63) stuck at logic '1'.

This address error example indicates an error in row address line A6 (connector pin 125) which affect some portion of the individual chips of the module. Since all address lines multiplex both rows and columns, an address error may affect ROW, COL (column) or ROW+COL. The bottom line further shows which data bits in the current bank are affected by the detected error. This allow an advance user (e.g. a memory technician who can repair the module) to identify individual defective chips on the module. All DQ lines are divided into 4-bit groups called NIBBLES, and the hex number indicate which nibbles are affected by the address errors. In the above example, the nibbles code ...0303 is translated to ... 01100000011, indicating problems in nibbles 0,1,8 and 9.

Basic Test Results

The following screen shows the first summary screen following a successful Basic Test with another module:

In this example, a DDR 512MB module, organized as 64Mx64 was tested at 266MHz. The module was of the Unbuffered type (UBF message), tested at 2.5V (like all DDR devices), and it uses 3 differential clock pairs.

During Basic Test, RAMCHECK tests the operation of the three Burst Length available in DDR devices - 2, 4, and 8. Unlike older SDRAM, new DDR devices do not support Full Page Burst. The following screen shows a summary screen indicating that BL (Burst Length) was tested OK:

During the Basic Test, RAMCHECK interrogates the SPD of the module to read the maximum declared frequency at CAS LATENCY (CL) 2 and 2.5:

The above example shows the reading from a typical PC2700/PC333 module. Such a module can reach 333MHz operation only in the slower CL2 mode.


You can change test parameters on the fly by pressing F2 during Basic Test to reach the familiar Change-On-The-Fly menu:

Please note that the Refresh override feature is not supported on DDR adapters and is included on this menu in conformance with the legacy test flow of the RAMCHECK system for SDRAM and EDO/FPM tests.

Selecting F1 will activate the Frequency setup menu:

This menu is similar to the SDRAM frequency setup menu. In this example the user selects a frequency 248MHz. Pressing F1 will restart Basic Test at 248MHz. Currently, the maximum frequency for the DDR test is set to 266MHz, but higher frequencies will be released in the near future.

Any change done via the Change-On-The-Fly menu is relevant during the current test. Permanent setup changes can be done via the regular Setup menu, which is activated by pressing F2 during STANDBY.

Module's use of DQS and DM control lines

DDR memory devices use data read/write strobe signals (DQS) as well as Data Mask (DM) signals for masking write activity on the selected chip. The DQS line controls the transfer of data from and to the memory device. When the DM signal is set high, the attached DDR device will not accept data which is written to it, that is, the written data is masked out from changing the memory device contents. The 184-pin connector includes either 9 DQS line and 9 DM lines or only 18 DQS lines.

Most DDR module are made of x8 type DDR chips and they are wired to use 9/8 DQS lines (9 for x72 ECC DIMMs, only 8 for x64 DIMMs). They also use 9/8 DM lines. Such modules are identified in RAMCHECK's Test Log with the line "DQS:08..0 DM:08..0" as depicted in the following screen:

Some Registered modules which are made of x4 type DDR chips are wired to 18/16 DQS lines (18 for x72 ECC DIMMs, only 16 for x64 DIMMs). The DM control line of the DDR chips of such modules are disabled by a fixed connection to ground. Such modules are identified in RAMCHECK's Test Log with the line "DQS:17..0" as shown in the following screen:

Some examples for modules with 18 DQS control lines include Samsung p/n M383L6420DTS and Micron Technology p/n MT18VDDT3272G.


The EXTENSIVE TEST for DDR is similar to our regular SDRAM test. Currently, the following test phases are performed:

  • Voltage Cycling
  • Voltage Bounce
  • March Up/Down
  • Chip Heat
  • Final Test


The AUTO-LOOP test uses changing patterns to burn-in the module and to detect cell interferences.


The DDR S.O. DIMM Converter (p/n INN-8668-6-1) allows testing of 200-pin DDR S.O. DIMM (PC333/266/200) on the DDR-184 PIN Adapter (p/n INN-8668-6).

200-pin SODIMM tester

The converter is made in the shape of a standard 184-pin DIMM module, but without the center key. It has special electronics for RAMCHECK's auto-detection, and it is designed for low noise and short signal connections.


Place the converter on a flat surface that is covered with a proper anti-static sheet. Insert the 200-pin SO DIMM into socket J2, making sure that the module's pin-1 is facing left. Socket J2 is similar to the standard laptop sockets, and it has metal latch to insure proper retention of the module in place. We have selected the AMP gold plated sockets as the best available in the market. Once inserted, the module surface locks in parallel to the converter board, with the module's front side aligning with the converter's front side.

Insert the converter into the DDR adapter's 184-pin test socket as if it was a regular DDR module, making sure that pin-1 faces left. Press F1 to start the test, which generally follows the regular DDR test flow as outlined above.

At the end of the test (RED power LED must be off), remove the converter and place it on the protected flat surface for removal of the tested S.O. DIMM module.

The converter is auto detected, and RAMCHECK's standby message should continue to indicate a 200-pin S.O. DIMM until a regular 184-pin DDR module is tested.

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