Describes the type of DUT (Device Under Test) that is being tested. In this
|BANK BITS DETECTED: BANK 1: CB DQ63-32 DQ31-0 00
BANK 2: CB DQ63-32 DQ31-0 00 FFFFFFFF FFFFFFFF
A new feature added to firmware version 2.21 and
higher for SDRAM devices only. It gives you a brief description of the
structure of the SDRAM device by mapping the DQ and CB (Parity) bits by the
module's individual banks. This feature is very useful in troubleshooting SDRAM
Modules with severe or multiple errors. For more information on this feature
please read: http://www.innoventions.com/ramcheck/rc_ap1.htm
The test phase use by the RAMCHECK.
TEST AT 3.3V
The SDRAM device is being tested at 3.3
Shows the size of the SDRAM device in both JEDEC
notation and overall size.
||CHIP SIZE: 4x2Mx16
Shows the size of the individual SDRAM chips of
the SDRAM module in JEDEC notation.
ROW/9 COL ADDR.
Shows the number of rows and columns detected by
Shows that the refresh rate is in Auto mode which will use the RAMCHECK's
default value of 50ms.
||BANKS: 2 -S:0+1+2+3 DQMB:0+1+2+3+4+5+6+7
Shows a brief description of the structure of the SDRAM device. Similar to the
"BANKS BITS DETECTED" shown above, but by displaying the number of
banks and individual control lines that were detected by the RAMCHECK.
SPD=JEDEC PC133 SPD=NO 100MHz @ CL2
Anytime you see "SPD=" in the test log,
it always refers to the information read directly from the SPD chip on the
SDRAM module. This is programmed by the module's manufacturer. In this case the
SPD claims that the module is a PC-133 and the CAS Latency 2 is not supported.
For more information on the PC133 and CAS Latency 2 SPD determination please
read the following information:
You can also view the "ACCESS TIME FROM CLK", "CL2@100MHz="
and "SPEED TEST RESULT" described below to see if the SPD information
compares with the RAMCHECK's test results.
||SDRAM 168P DIMM
Shows the form factor of the SDRAM device. In this
instance a 168-pin DIMM.
TEST TABLE #17 CODE=0067
The "TEST TABLE" and "CODE"
indications are used as part of our factory development to identify certain
characteristics of the SDRAM module. This identifications can also be used as a
form of comparison to other SDRAM modules.
The RAMCHECK detected the SDRAM
module type as conforming to the JEDEC standard for Unbuffered configurations.
Other types may include Registered, etc.
The RAMCHECK detected that this SDRAM module does
not have (ECC) Error Correction Code wiring. If "ECC=Y" was displayed
then ECC was detected.
The RAMCHECK detected the use of all four clock inputs.
SINGLE WRITE OK
Refers to one of the burst operation modes of the SDRAM device. The burst
lengths applied only to the read cycles. All write cycles are single write
Indicates the maximum frequency page burst of the SDRAM module, in this case
||ACCESS TIME FROM CLK Tac (CL=3): 4.5nS Tac
(CL=2): 4.5nS Tac RANGE:
Shows the measurements of tAC (access time from clock) for CAS Latency 2 &
3. For more information on the tAC measurements and the tAC range please read
the following: http://www.innoventions.com/ramcheck/rc_ap13.htm
Shows that the RAMCHECK passed this function. More details are available at:
TEST RESULT: TEST=PC133 RANGE FINAL SPEED:133MHz
The Ramcheck has determined that this SDRAM module is within
PC133 specifications with its ending Basic Test speed as being
||BASIC TEST OK TIME: 00:17.2
Shows the SDRAM module passed the Basic Test along with the test time.