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RAMCHECK Application Note

and PC-133 Determination


--Created 3-8-2005

Most SDRAM chips have the speed rating (in nanoseconds) stamped on them. This speed represents the "tCLK" or the minimum clock cycle time. To calculate the maximum frequency in megahertz you simply take the reciprocal (1/x) of this speed stamp. However, it is critical to note that the chip's maximum frequency does not conform directly to the PC bus frequency. The table below is a list of speed ratings typically seen on SDRAM chips.
Cycle Time in nanoseconds Maximum Frequency
-12 83 MHZ
-10 100 MHZ
-8 125 MHZ
-7.5 133 MHZ
-7 143 MHZ
-6 167 MHZ
-5 200 MHZ

It can be easy to misread this information. If the chips on an SDRAM module are stamped "-10" (which has a maximum frequency of 100 MHZ), you may assume that it is a PC-100 module. It is definitely not so for SDRAM technology. We first need to allow a margin called "setup time" that insures the data is ready before the clock changes. Some additional timing allowances must also be considered when mounting these chips on printed circuit boards or modules due to trace lengths, other components connected to the IO pins of the chips, and so forth.

For example, a PC-100 SDRAM module typically has chips stamped with "-8" (which has a maximum frequency of 125 MHZ) to allow applications running a bus speed at 100 MHZ. In general, you always use an SDRAM chip that has a maximum frequency significantly faster than the bus speed of the application. Therefore, if a chip is marked -5 (200MHz), do not expect it to test on RAMCHECK at 200MHz - it will run at substantially lower speed.

Another important timing parameter to consider is called the tAC, which is the access time from the clock. The tAC is dependent on the CAS Latency setup. For CAS Latency 3, first data is valid at the rising edge of the third clock from the read command. For CAS Latency 2, first data is valid at the rising edge of the second clock from the read command.

Please note that the newer DDR technology is different since there are two data accesses per clock. DDR modules are explicitly marked with the DDR data rate (and other parameters like CAS Latency, tRCD ant tRP).

The following drawing shows the CAS Latency in a simplified way. It is assumed that the bank ACTIVE command, which is needed to start any SDRAM activity, has been properly initiated prior to the READ command. The read data can be a burst of 1,2,4,8, or even a full page of data, depending upon the SDRAM setup. Therefore, CAS Latency determines when the first data is valid.

As shown in the drawing, for CAS Latency 2, the tAC parameter is the time from the rising edge of the first clock after the READ command to the time that first data is valid. For CAS Latency 3, the tAC parameter is the time from the rising edge of the second clock after the READ command to the time that first data is valid. The table below represents the tAC limits based on Intel specifications.

  PC-66 PC-100 PC-133
Cas Latency 2 9 ns or faster 6 ns or faster  
Cas Latency 3 9 ns or faster 6 ns or faster 5.4 ns or faster

RAMCHECK tAC Measurements

At the start of the Basic test the RAMCHECK measures the module's tAC at CAS Latency 2 and CAS Latency 3. If the module has two banks, the RAMCHECK takes the slower measurements (higher access time in ns) into account. The program uses specific margins to determine if the tested module exhibits tAC in the range of the PC-133, PC-100 or the PC-66 standard. These measurements are displayed in the test log which you can view after the Basic test has been completed. You can also view this information by pressing "F5" any time during the "Basic Test". The screen captures below from the RAMCHECK test log are examples of this tAC information.

The RAMCHECK program uses these tAC measurements in conjunction with the SPD information to determine the test frequency of the module during the Basic test. A module which indicates a tAC Range of <PC-100> will be run at 100MHz, while a module with a tAC Range of <PC-66> will be run at 83MHz. Other timing problems of the module may cause it to drift to lower speeds during the Basic test or subsequent tests.

Please note that you can still override the speed. For example, you can cause a module with a tAC measurement of 8nS to run at 100MHz by using Test Setup or the Change-on-the-Fly feature to override. Of course, such a module cannot meet the PC-100 specification of 6nS. Therefore, the fact that a module may run on the RAMCHECK at 100MHz does not imply that the module is indeed PC-100 compliant. Some modules which are not certified for PC-100 (and their SPD indicates that they are intended for PC-66) may still score within the <PC-100> range on the RAMCHECK, as their access times are indeed quite fast. However, such modules may still exhibit unfavorable results in an actual PC-100 application, as there are several other factors involved in PC-100 compliance.

An exact measurement of the tAC requires the use of a very expensive tester with a variable temperature oven, sub-nanosecond accuracy, and complex capabilities to compensate for all loading effects. The RAMCHECK has an inherent inaccuracy of about +/- 0.5nS in determining the tAC measurements. Therefore, we are using the notion of tAC RANGE to allow for such measurement inaccuracies and to encourage the user to consider the actual tAC measurements.


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