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RAMCHECK Application Note

SDRAM SPD Data Standards

--Revised 5-10-2005

The Serial Presence Detect (SPD) device is a small 8-pin 256-byte EEPROM chip, mounted on a 168-pin DIMM module or a 144-pin SO DIMM module. It contains important information about the module's speed, size, addressing mode and various other parameters, so that the motherboard memory controller (chipset) can better access the memory device. The SPD contents are controlled by the JEDEC standard. The Intel PC-100 standard uses the same data content, but includes Intel's distinct settings in the bytes designated for Vendor Specific entries. The PC133 standard was developed by a group of companies led by Via Technologies, IBM Microelectronics, Micron Semiconductor, NEC and Samsung. It is essentially based on the INTEL PC-100 specification with the enhancement of 133MHz operation at a Cas Latency of 3 (CL=3) and access time from clock (Tac) of 5.4nS.

This application note illustrates the JEDEC standard as well as the variance that is used by Intel and the PC133 group for 168-pin SDRAM DIMMs. It further explains RAMCHECK's screen indications regarding SPD data.


The following are the SPD contents assigned for 168-pin SDRAM DIMMs as listed from the JEDEC standard No. 21-C. For ease of use, we have added typical CAS Latency values to the table itself.

Byte Number Function Notes
0 Defines # bytes written into serial memory at module manufacturer. 1,8
1 Total # bytes of SPD memory device. 2,8
2 Fundamental Memory Type (FPM, EDO, SDRAM…). 8
3 # Row Addresses on this assembly. 3,8
4 # Column Addresses on this assembly. 8
5 # Module Banks on this assembly. 8
6 Data width on this assembly. 8
7 Data width continuation. 8
8 Voltage interface standard of this assembly. 8
9 SDRAM Cycle Time at maximum supported CAS Latency (CL), CL=X. Typically this value is for CL=3. 4,8
10 SDRAM Access from Clock at maximum supported CL=X. Typically this value is for CL=3. 4,8
11 DIMM Configuration type (Non-parity, Parity, ECC). 8
12 Refresh Rate/Type. 4,5,8
13 SDRAM width, Primary DRAM. 8
14 Error checking SDRAM data width. 8
15 Minimum Clock delay, Back to Back Random Column Address. 8
16 Bursts lengths supported. 8
17 # Banks on each SDRAM device. 4,8
18 CAS # Latencies supported. 4,8
19 CS# Latency. 4,8
20 Write Latency. 4,8
21 SDRAM module attributes. 8
22 SDRAM device attributes: Genera.l 8
23 Minimum Clock cycle Time at CL X-1. Typically this value is for CL=2. 4,8
24 Maximum Data access Time from Clock @ CL X-1. Typically this value is for CL=2. 4,8
25 Minimum Clock cycle Time at CL X-2. Typically this value is for CL=1 which is usually not supported. 4,9
26 Maximum Data Access Time from Clock at CL X-2. Typically this value is for CL=1 which is usually not supported. 4,9
27 Minimum Row Precharge Time. 4,8
28 Minimum Row Active to Row Active delay. 4,8
29 Minimum RAS to CAS delay. 4,8
30 Minimum RAS pulse width. 4,8
31 Module Bank Density. 8
32-61 Superset Information (may be used in future).
62 SPD Revision. 8
63 Checksum for bytes 0-62. 8
64-71 Manufacturer's JEDEC ID code. 6,9
72 Manufacturing location. 6,9
73-90 Manufacturer's Part Number. 6,9
91-92 Revision Code. 6,9
93-94 Manufacturing Date. 6,9
95-98 Assembly Serial Number. 6,9
99-125 Manufacturer Specific Data. 6,9
126 Vendor Specific. 6,8,10
127 Vendor Specific. 6,8,10
128-255 Open for Customer Use. 7


  1. This will be programmed as 128 bytes for the 168 pin DIMM Module.
  2. This must be programmed as 256 bytes. 256 byte EEPROMs will be used for SPD on 168-pin SDRAM DIMMs.
  3. High order bit defines if assembly has "redundant" addressing (if set to "1", highest order RAS# address must be re-sent as highest order CAS# address).
  4. From data sheet.
  5. High order bit (MSB) is Self Refresh "Flag". If bit seven is "1", assembly supports self refresh.
  6. JEDEC specifies that these bytes are optional.
  7. Module suppliers will need to assure that these bytes are open for reads/writes by customer.
  8. Required for Intel specifications.
  9. Optional for Intel specifications.
  10. See below for further information on how Intel uses these two bytes 126 and 127.


Byte 126 - Intel specification for frequency

The JEDEC standard calls for Byte 126 and Byte 127 to be vendor specific, Intel uses these two bytes in the following manner.

This byte defines the clock frequency of the Intel SDRAM DIMM specification.

Intel Specification Frequency Hex Value
66 MHz 66h
100 MHz 64h
PC-133 64h or 85h

For 100MHz support, this byte should be programmed to 64h. For 66MHz support, this byte should be programmed to 66h, which is required for backward compatibility with existing BIOS code.

Byte 127 - Intel Specification details for 100MHz Support

This byte defines the SDRAM component and Clock interconnection details for the DIMMs as defined:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 21 Bit 1 Bit 02
CLK0 CLK1 CLK2 CLK3 Junction Temp CAS Latency=3 CAS Latency=2 Intel "Concurrent AP"
1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0
1Bits 2 and 3 are "preserved" for backward compatibility with existing BIOS code
2For a complete definition of "Intel Concurrent AP" functionality, consult Intel's PC-SDRAM specification
  • Bit 7=1: CLK0 is connected on the DIMM
  • Bit 7=0: CLK0 is not connected on the DIMM
  • Bit 6=1: CLK1 is connected on the DIMM
  • Bit 6=0: CLK1 is not connected on the DIMM
  • Bit 5=1: CLK2 is connected on the DIMM
  • Bit 5=0: CLK2 is not connected on the DIMM
  • Bit 4=1: CLK3 is connected on the DIMM
  • Bit 4=0: CLK3 is not connected on the DIMM
  • Bit 3=1: Component tested to case temperature A (value TBD)
  • Bit 3=0: Component tested to case temperature B (value TBD)

Bit 2 and Bit 1=CL3 and CL2 support as shown:

Performance Grade Hex Value (Bits 2-1)
CAS Latency 3 04
CAS Latency 2 06
  • Bit 0=1: It supports Intel defined Concurrent Auto-precharge
  • Bit 0=0: It does not support Intel defined Auto-precharge

Typical PC-100 Timing Values

The following values appears in most PC-100 modules:

For CAS Latency 3, byte 9=A0h to indicate 10nS cycle time, and byte 10=60h to indicate 6nS access time from clock. Please note that the letter 'h' after 'A0' or '60' is used to indicate hexadecimal values.

If the high speed CAS Latency 2 is supported (as required, for example, for the AMD Athlon processors), byte 23=A0h to indicate a 10nS cycle time (at CL=2), and byte 24=60h to indicate a 6nS (or=65h to indicate 6.5nS) access time from clock. However, we have found that byte 24 may be left at 0 by some manufacturers.

PC-133 Values

Tthe SPD data of a PC133 modules is similar to the PC-100 SPD data, with the exception of byte 9 (SDRAM device cycle time CL=3) set to 75h (7.5nS) and byte 10 (SDRAM device access time from clock at CL=3) set to 54h (5.4nS).

In many PC-133 modules in the market we have found that the CAS Latency 2 speed (byte 23 and 24) are left at 0, as PC-133 is essentially supported for CAS Latency 3.

Byte 126 may be marked with 64h like a PC-100 module, or by 85h, as shown in the table above.

RAMCHECK identifies the setting for the Intel standard by reading Byte 126. RAMCHECK's display will reflect this setting in the test log, and also in the form of a summary screen after the Basic Test as shown below.

Screen Image Screen Image
Test Log Summary Screen

Other messages will include the following:


Please note that whenever RAMCHECK uses the notation "SPD=", it refers to information read from the SPD chip. As newer firmware revisions are developed, you will note that RAMCHECK will measure additional characteristics of the memory device. The acquired values will then be compared to the SPD data that is read and subsequently be displayed in the test log for comparative purposes.


For more information, please call us at (281) 879-6226 M-F 9:00-5:00 CST, or send your E-mail to support@innoventions.com, or fax your message to (281) 879-6415. Please remember to include your phone and e-mail.

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