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SIMCHECK Application Note


One of the more useful tools of SIMCHECK II's program is the Test Log that continually runs and is updated throughout the test procedure. The test log records all results acquired from each of the test phases run and logs detailed information regarding any errors that occurred.

  Test Log

The test log can be accessed during Standby Mode by pressing F4, and once opened, it can be reviewed by pressing F3 and F4 to scroll through a virtual window of codes and test results. This application note helps to define what the test log codes are and how they should be interpreted.

As shown in the above test log image, the first screen of the test log window shows the module's overall size and configuration, and what voltage was used to test it; in this example a 128M module was tested at 5V.

Note that some test details are unique to SDRAM modules, while others are unique to EDO/FPM.
Test Log Image
The subsequent Test Log window will provide information on the architecture of the chips used in the device under test (DUT). This screen shows a module using chips organized as 4x8Mx8. Its speed was 133MHz and SIMCHECK detected the use of all four clock inputs.
Note that the speed for SDRAM devices is displayed in megahertz (MHz), while EDO/FPM devices are measured in nanoseconds (nS).
Test Log Image
The "Test =" indicates that SIMCHECK II has determined that the DUT is a PC-133 module with its ending Basic Test speed as being 133MHz. The ending test time is also displayed. Please review Application Note 18 for further information on determining PC-133 compliance.
Test Log Image

Test Log Image
A message indicating the number of banks used and which control signals were active. In SDRAM devices, -S signals and DQMB lines correspond the the RAS and CAS lines, respectively, of standard DRAM. Serial Presence Detection (SPD) settings are also listed. SIMCHECK II provides full SPD Management for editing, saving, and programming SPD data.
The second screen indicates that SIMCHECK II detected a 72-pin SIMM with 4 Column Address Signals (CAS) in the DUT. Similar information is also given for (RAS) Row Address Signals (not shown). The PRD information indicates that all PResence Detection jumper settings are all set to 0.
The Table #5, Code 36 indications found in either type of device are used as part of our factory development to identify certain characteristics of the module. This identifications can be used as a form of comparison to other modules where a compatibility issue may arise.
Test Log Image The module type is displayed as conforming to the JEDEC standard for x36-bit configurations. Other types may be JEDEC x72, Unbuffered, Registered, etc. The module does not have (ECC) Error Correction Code wiring is a Fast Page Mode (FPM) DRAM. In this case, a Data Bit error was encountered.
Test Log Image The time of the error is recorded, with the corresponding written pattern and the pattern that was read.
Test Log Image The address location where the error was encountered is displayed, as well as which function caught the error. The state of each control signal is given. In this case, the RAS signal state was 5 (a binary 0101), corresponding to RAS 0 and RAS 2 being active.
Test Log Image The Mask Properties, Bank Command, and Bus code are shown to detail how we internally map the processor to the Device under Test. This information is mostly for product development, but may be requested by our Tech Dept. in case of a compatibility issue. Further error information can be acquired by reviewing Application Note 9.

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