This application note discusses SIMCHECK internal timing tables, relative refresh, and relative spikes. It also provides more details on the information in the SIMCHECK Owner's Manual.
NOTE: THIS DOCUMENT IS FOR CONTROLLED CIRCULATION ONLY AS IT PERTAINS TO CONFIDENTIAL INFORMATION!
SIMCHECK SPEED TESTING METHODOLOGY AND ITS INTERNAL TIMING TABLES
SIMCHECK's program digitally controls the timing parameters of the tested memory devices with a proprietary dynamic algorithm that is outlined below. In addition to generating the Access Time Data-Latch signal (from -RAS or -CAS), it can change the delay between -CAS to -RAS (TRCD), and it can select different Row/Column Address Hold/Setup Times (TRAH, TASR, TCAH and TASC). In its automatic [default] mode, SIMCHECK first measures the -RAS Access time and then it continuously adjusts it under varying test conditions (different data patterns, changing voltages, voltage-bounce tests, ground-bounce and simulated spike/noise). With its advanced set-up mode, the user can set-up fixed speed and/or fixed size.
When the automatic speed algorithm encounters a memory error, it first changes the timing parameters (by using different internal timing tables associated with the same access time). If all timing parameters are attempted and the error persists, the algorithm increases the Access Time. If the error is not eliminated at higher speeds, SIMCHECK will identify it as an actual memory failure (failed bit/s identification and error location are shown). Using its CHIP-HEAT mode, the tested memory is warmed up (during the EXTENSIVE TEST MODE), which usually results at slower speeds. Sensitivity to the artificial ground-bounce that SIMCHECK creates may result in stronger speed drift.
When SIMCHECK is preset with the fixed speed algorithm (SPEED OVERRIDE), the program does not change the access time. It just changes the timing tables associated with the same access time so that several timing parameters are being attempted before an error is identified.
The following provides some more details about the timing parameters used by SIMCHECK. They are based on a thorough survey of published data sheets from all major DRAM manufacturers.
Memory Initialization - initial pause (-RAS, -CAS, -W held at '1') for 250 micro- seconds followed by 9 -RAS cycles.
When testing between 20nS-150nS, SIMCHECK uses the following timing parameters:
| -RAS ACCESS | TRCD | TASR | TRAH | TASC | TCAH | ||
| 20-60nS | 10-15nS | > 10nS | 2-10nS | 0-10nS | > 50nS | ||
| 50-100nS | 25nS | > 10nS | 10-20nS | 0-10nS | > 50nS | ||
| 100-150nS | 40-50nS | > 20nS | 25-35nS | 10-15nS | > 70nS |
DYNAMIC DRAM REFRESH
SIMCHECK uses refresh values which are based on the industry standard 8mS/16mS with heuristic extrapolation from room temperature to Worst Case Temperature (e.g. x2 per each 10 degree Celsius above room temperature). Memory devices which pass the Basic Test meet the standard refresh requirements.
RELATIVE REFRESH FIGURE
Extensive experimentation by INNOVENTIONS and other parties have indicated that memory devices typically have low cell leakage which allow a significantly reduced refresh cycle. In fact, many motherboard's chip-set manufacturer take this into account during their automatic "Extended Refresh" mode.
INNOVENTIONS proprietary Relative Refresh was developed to provide SIMCHECK's users with a quality comparison between memory products from various vendors. Since, as described in the manual, SIMCHECK's test for the Relative Refresh goes far beyond the JEDEC specification for memory devices, a low figure of Relative Refresh is by no means an indication of failure. Over the years, many SIMCHECK users have been able to correlate intermittent memory problems with low Relative Refresh figures (or also with low Relative Spikes figures).
During Relative Refresh, SIMCHECK fills a large DRAM block with a checker pattern (e.g. 1010101..). Then it stops all refresh activity during a delay period. At the expiration of this delay period, SIMCHECK verifies the data in the entire block. If the data is fully retained, SIMCHECK repeats the process with a double delay period. If the data is corrupted, the test end and a Relative Refresh figure indicates the time that the module retained data without refresh in accordance with the following table:
Relative Refresh Figure No-refresh Data Retention Period
0 N/A, as the module passed BASIC TEST
1 < 128mS
2 128mS
3 256mS
4 512mS
5 1,024mS
6 2,048mS
7 4,096mS
8 8,192mS
9 16,384mS
RELATIVE SPIKES FIGURE
The Relative Spikes test subjects the memory device to accelerated voltage spikes which are far beyond the JEDEC specification. Of course, the device under test is kept away from the absolute maximum rating range to avoid damage. As such, a low Relative Spikes figure does not indicate a DRAM failure. Yet, the figure does provide some comparison between various brand of memory devices.
During Relative Spikes, SIMCHECK fills a larger block of DRAM with a checker pattern and then it creates a controlled voltage spike by setting the voltage to 5V, 3V, and back to 5V. If data is retained, we repeat the process with one added pulse. After 3 spikes (that is at Relative Spikes figure of 4 or above) SIMCHECK makes the spike to go deeper to 1.5V. After 6 spikes, the voltage goes from 1.5V to 6V and then slides down to 5V. In addition, the width of the voltage spike is incremented as the number of spikes increase. Since SIMCHECK's red LED is connected to the module power line, the actual spikes are actually indicated.
